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general description the max1544 is a dual-phase, quick-pwm, step-down controller for amd hammer cpu core supplies. dual-phase operation reduces input ripple current requirements and output voltage ripple while easing component selection and layout difficulties. the quick- pwm control scheme provides instantaneous response to fast load-current steps. the max1544 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output capacitance requirements. the max1544 is intended for two different notebook cpu core applications: stepping down the battery directly or stepping down the 5v system supply to create the core voltage. the single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. alternatively, two-stage con- version (stepping down the 5v system supply instead of the battery) at a higher switching frequency provides the minimum possible physical size. the max1544 complies with amd? desktop and mobile cpu specifications. the switching regulator fea- tures soft-start and power-up sequencing, and soft-shutdown. the max1544 also features indepen- dent four-level logic inputs for setting the suspend volt- age (s0?1). the max1544 includes output undervoltage protection, thermal protection, and voltage regulator power-ok (vrok) output. when any of these protection features detect a fault, the controller shuts down. additionally, the max1544 includes selectable overvoltage protection. the max1544 is available in a low-profile, 40-pin 6mm x 6mm thin qfn package. for other cpu platforms, refer to the pin-to-pin compatible max1519/max1545 and max1532/max1546/max1547 data sheets. applications amd hammer desktop or notebook pcsmultiphase cpu core supply voltage-positioned step-down converters servers/desktop computers features ? dual-phase, quick-pwm controller ? ?.75% v out accuracy over line, load, and temperature (1.3v) ? active voltage positioning with adjustable gainand offset ? 5-bit on-board dac: 0.675v to 1.55v outputadjust range ? selectable 100khz/200khz/300khz/550khzswitching frequency ? 4v to 28v battery input voltage range ? adjustable slew-rate control ? drives large synchronous rectifier mosfets ? selectable output overvoltage protection ? undervoltage and thermal-fault protection ? power sequencing and timing ? selectable suspend voltage ? soft-shutdown ? selectable single- or dual-phase pulse skipping max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ________________________________________________________________ maxim integrated products 1 v dd dlmlxm bstm d1 d2 d3 vrokd0 dhm sus s0s1 ofs ref ilim v cc ton time 12 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20 4039 38 37 36 35 34 33 32 31 3029 28 27 26 25 24 23 22 21 fb oain- oain+ ovp d4 cci gnds ccv gnd csncmn cmp v+ bsts lxs dhs dls pgnd csp thin qfn max1544 top view shdn skip pin configuration ordering information 19-2745; rev 1; 9/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max1544etl -40 c to +100 c 40 thin qfn 6mm ? 6mm quick-pwm is a trademark of maxim integrated products, inc.hammer is a trademark of amd. downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ..............................................................-0.3v to +30v v cc to gnd ..............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v skip , sus, d0 d4 to gnd.......................................-0.3v to +6v ilim, fb, ofs, ccv, cci, ref, oain+, oain- to gnd.........................................-0.3v to (v cc + 0.3v) cmp, csp, cmn, csn, gnds to gnd ......-0.3v to (v cc + 0.3v) ton, time, vrok, s0 s1, ovp to gnd ....-0.3v to (v cc + 0.3v) shdn to gnd (note 1)...........................................-0.3v to +18v dlm, dls to pgnd ....................................-0.3v to (v dd + 0.3v) bstm, bsts to gnd ..............................................-0.3v to +36v dhm to lxm ...........................................-0.3v to (v bstm + 0.3v) lxm to bstm............................................................-6v to +0.3v dhs to lxs..............................................-0.3v to (v bsts + 0.3v) lxs to bsts .............................................................-6v to +0.3v gnd to pgnd .......................................................-0.3v to +0.3v ref short-circuit duration .........................................continuous continuous power dissipation (t a = +70 c) 40-pin 6mm ? 6mm thin qfn (derate 23.2mw/ c above +70 c) ...............................1.860w operating temperature range .........................-40 c to +100 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = 0? to +85? , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units pwm controller battery voltage, v+ 4 28 input voltage range v cc , v dd 4.5 5.5 v dac codes 1v -10 +10 dc output voltage accuracy(note 2) v+ = 4.5v to 28v,includes load regulation error dac codes from0.60v to 1v -15 +15 mv line regulation error v cc = 4.5v to 5.5v, v+ = 4.5v to 28v 5 mv i fb , i gnds fb, gnds -2 +2 input bias current i ofs ofs -0.1 +0.1 ? ofs input range 02 v ? v out / ? v ofs; ? v ofs = v ofs, v ofs = 0 to 1v -0.129 -0.125 -0.117 ofs gain a ofs ? v out / ? v ofs; ? v ofs = v ofs -v ref, v ofs = 1v to 2v -0.129 -0.125 -0.117 v/v gnds input range -20 +200 mv gnds gain a gnds ? v out / ? v gnds 0.97 0.99 1.01 v/v 1000khz nominal, r time = 15k 900 1000 1100 500khz nominal, r time = 30k 460 500 540 250khz nominal, r time = 60k 225 250 275 time frequency accuracy f time shutdown, r time = 30k 125 khz note 1: shdn may be forced to 12v for the purpose of debugging prototype boards using the no-fault test mode, which disables fault protection and overlapping operation. downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units ton = gnd(550khz) 155 180 205 ton = ref(300khz) 320 355 390 ton = open(200khz) 475 525 575 on-time (note 3) t on v+ = 12v,v fb = v cci = 1.2v ton = v cc (100khz) 920 1000 1140 ns ton = gnd 300 375 minimum off-time (note 3) t off ( min ) ton = v cc , open, or ref 400 480 ns bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point, oain- = fb, v oai n + = 1.3v 1.70 3.20 ma quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point <1 5 ? quiescent battery supply current(v+) i v+ measured at v+ 25 40 ? shutdown supply current (v cc ) measured at v cc , shdn = gnd 4 10 a shutdown supply current (v dd ) measured at v dd , shdn = gnd <1 5 a shutdown battery supply current(v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v <1 5 ? reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.990 2.000 2.010 v reference load regulation ? v ref i ref = -10? to 100? -10 +10 mv fault protection skip = v cc , measured at fb with respect to unloaded output voltage 13 16 19 % output overvoltage protection threshold v ovp skip = ref or gnd 2.00 v output overvoltage propagation delay t ovp fb forced 2% above trip threshold 10 ? output undervoltage protection threshold v uvp measured at fb with respect to unloadedoutput voltage 67 70 73 % output undervoltage propagation delay t uvp fb forced 2% below trip threshold 10 ? lower threshold (undervoltage) -12 -10 -8 vrok threshold measured at fbwith respect to unloaded output voltage upper threshold (overvoltage) skip = v cc +8 +10 +12 % downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units output undervoltage fault and vrok transition blanking time (note 4) t blank measured from the time when fb reachesthe voltage set by the dac code; clock speed set by r time 24 clks vrok startup delay measured from the time when fb firstreaches the voltage set by the dac code after startup 357m s vrok delay t vrok fb forced 2% outside the vrok tripthreshold 10 ? vrok output low voltage i sink = 3ma 0.4 v vrok leakage current high state, vrok forced to 5.5v 1 a v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 90mv, pwmdisabled below this level 4.0 4.25 4.4 v thermal-shutdown threshold t shdn hysteresis = 10 c 160 c current limit and balance current-limit threshold voltage(positive, default) v limit cmp - cmn, csp - csn; ilim = v cc 28 30 32 mv v ilim = 0.2v 8 10 12 current-limit threshold voltage(positive, adjustable) v limit cmp - cmn, csp - csn v ilim = 1.5v 73 75 77 mv current-limit threshold voltage(negative) v limit ( neg ) cmp - cmn, csp - csn; ilim = v cc , skip = v cc -41 -36 -31 mv current-limit threshold voltage(zero crossing) v zero cmp - cmn, csp - csn; skip = gnd 1.5 mv cmp, cmn, csp, csn inputranges 02 v cmp, cmn, csp, csn inputcurrent v csp = v csn = 0 to 5v -2 +2 ? secondary driver-disablethreshold v csp 3v cc - 1 v cc - 0.4 v ilim input current i ilim v ilim = 0 to 5v 0.1 200 na current-limit default switchoverthreshold v ilim 3v cc - 1 v cc - 0.4 v current-balance offset v os ( ibal ) (v cmp - v cmn ) - (v csp - v csn ); i cci = 0, -20mv < (v cmp - v cmn ) < 20mv, 1.0v < v cci < 2.0v -2 +2 mv downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 5 electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units current-balancetransconductance g m ( ibal ) 400 ? gate drivers dh_ gate-driver on-resistance r on(dh) bst_ - lx_ forced to 5v 1.0 4.5 high state (pullup) 1.0 4.5 dl_ gate-driver on-resistance r on(dl) low start (pulldown) 0.4 2 dh_ gate-driver source/sinkcurrent i dh dh_ forced to 2.5v,bst_ - lx_ forced to 5v 1.6 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 5v 4 a dl_ gate-driver source current i dl ( source ) dl_ forced to 2.5v 1.6 a dl_ rising 35 dead time t dead dh_ rising 26 ns voltage-positioning amplifier input offset voltage v os -1 +1 mv input bias current i bias oain+, oain- 0.1 200 na op amp disable threshold v oain- 3v cc - 1 v cc - 0.4 v common-mode input voltagerange v cm guaranteed by cmrr test 0 2.5 v common-mode rejection ratio cmrr v oain+ = v oain- = 0 to 2.5v 70 115 db power-supply rejection ratio psrr v cc = 4.5v to 5.5v 75 100 db large-signal voltage gain a oa r l = 1k to v cc /2 80 112 db v cc - v fbh 77 300 output voltage swing |v oain+ - v oain- | 10mv, r l = 1k to v cc /2 v fbl 47 200 mv input capacitance 11 pf gain-bandwidth product 3 mhz slew rate 0.3 v/? capacitive-load stability no sustained oscillations 400 pf logic and i/o shdn input high voltage v ih 0.8 v shdn input low voltage v il 0.4 v shdn no-fault threshold v shdn to enable no-fault mode 12 15 v ovp input high voltage 2.4 v ovp input low voltage 0.8 v high 2.7 ref 1.2 2.3 three-level input logic levels sus, skip low 0.8 v logic input current shdn , skip , sus, ovp -1 +1 ? d0 d4 logic input high voltage 1.6 v downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 6 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units d0 d4 logic input low voltage 0.8 v d0 d4 input current d0 d4 -2 +2 ? high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0 s1 low 0.4 v four-level input current ton, s0 s1 forced to gnd or v cc -3 +3 ? electrical characteristics(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units pwm controller battery voltage, v+ 4 28 input voltage range v cc , v dd 4.5 5.5 v dac codes 1v -13 +13 dc output voltage accuracy(note 2) v+ = 4.5v to 28v,includes load regulation error dac codes from0.60v to 1v -20 +20 mv ofs input range 02 v ? v out / ? v ofs; ? v ofs = v ofs, v ofs = 0 to 1v -0.131 -0.115 ofs gain a ofs ? v out / ? v ofs; ? v ofs = v ofs -v ref, v ofs = 1v to 2v -0.131 -0.115 v/v gnds gain a gnds ? v out / ? v gnds 0.94 1.01 v/v 1000khz nominal, r time = 15k 880 1120 500khz nominal, r time = 30k 450 550 time frequency accuracy f time 250khz nominal, r time = 60k 220 280 khz ton = gnd(550khz) 150 210 ton = ref(300khz) 315 395 ton = open(200khz) 470 580 on-time (note 3) t on v+ = 12v,v fb = v cci = 1.2v ton = v cc (100khz) 910 1150 ns ton = gnd 380 minimum off-time (note 3) t off ( min ) ton = v cc , open, or ref 490 ns downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 7 electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units bias and reference quiescent supply current (v cc )i cc measured at v cc , fb forced above the regulation point, oain- = fb, v oai n + = 1.3v 3.2 ma quiescent supply current (v dd )i dd measured at v dd , fb forced above the regulation point 20 ? quiescent battery supply current(v+) i v+ measured at v+ 50 ? shutdown supply current (v cc ) measured at v cc , shdn = gnd 20 ? shutdown supply current (v dd ) measured at v dd , shdn = gnd 20 ? shutdown battery supply current(v+) measured at v+, shdn = gnd, v cc = v dd = 0 or 5v 20 ? reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.985 2.015 v fault protection output overvoltage protection threshold v ovp skip = v cc , measured at fb with respect to unloaded output voltage 13 19 % output undervoltage protection threshold v uvp measured at fb with respect to unloadedoutput voltage 67 73 % lower threshold (undervoltage) -13 -7 vrok threshold measured at fbwith respect to unloaded output voltage upper threshold (overvoltage) skip = v cc +7 +13 % vrok startup delay measured from the time when fb firstreaches the voltage set by the dac code after startup 3m s v cc undervoltage lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 90mv, pwmdisabled below this level 3.90 4.45 v current limit and balance current-limit threshold voltage(positive, default) v limit cmp - cmn, csp - csn; ilim = v cc 27 33 mv v ilim = 0.2v 7 13 current-limit threshold voltage(positive, adjustable) v limit cmp - cmn,csp - csn v ilim = 1.5v 72 78 mv current-limit threshold voltage(negative) v limit ( neg ) cmp - cmn, csp - csn; ilim = v cc , skip = v cc -30 -42 mv current-balance offset v os ( ibal ) (v cmp - v cmn ) - (v csp - v csn ); i cci = 0, -20mv < (v cmp - v cmn ) < 20mv, 1.0v < v cci < 2.0v -3 +3 mv gate drivers dh_ gate-driver on-resistance r on ( dh ) bst_ - lx_ forced to 5v 4.5 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 8 _______________________________________________________________________________________ electrical characteristics (continued)(circuit of figure 1, v+ = 15v, v cc = v dd = v shdn = v ton = v skip = v s0 = v s1 = v ovp = 5v, v fb = v cmp = v cmn = v csp = v csn = 1.3v, ofs = sus = gnds = d0 d4 = gnd; t a = -40 c to +100 c , unless otherwise specified.) (note 5) parameter symbol conditions min max units high state (pullup) 4.5 dl_ gate-driver on-resistance r on(dl) low start (pulldown) 2 voltage-positioning amplifier input offset voltage v os -2.0 +2.0 mv common-mode input voltagerange v cm guaranteed by cmrr test 0 2.5 v v cc - v fbh 300 output voltage swing |v oain+ - v oain- | 10mv, r l = 1k to v cc /2 v fbl 200 mv logic and i/o shdn input high voltage v ih 0.8 v shdn input low voltage v il 0.4 v high 2.7 ref 1.2 2.3 three-level input logic levels sus, skip low 0.8 v d0 d4 logic input high voltage 1.6 v d0 d4 logic input low voltage 0.8 v ovp input high voltage 2.4 v ovp input low voltage 0.8 v high v cc - 0.4 open 3.15 3.85 ref 1.65 2.35 four-level input logic levels ton, s0 s1 low 0.4 v note 2: dc output accuracy specifications refer to the trip level of the error amplifier. when pulse skipping, the output slightly rise s (<0.5%) when transitioning from continuous conduction to no load. note 3: on-time and minimum off-time specifications are measured from 50% to 50% at the dhm and dhs pins, with lx_ forced tognd, bst_ forced to 5v, and a 500pf capacitor from dh_ to lx_ to simulate external mosfet gate capacitance. actual in- circuit times may be different due to mosfet switching speeds. note 4: the output fault-blanking time is measured from the time when fb reaches the regulation voltage set by the dac code.during normal operation (sus = gnd), the regulation voltage is set by the vid dac inputs (d0 d4). during suspend mode (sus = ref or high), the regulation voltage is set by the suspend dac inputs (s0 s1). note 5: specifications to t a = -40 c and +100 c are guaranteed by design and are not production tested. downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 9 output voltage vs. load current (v out = 1.50v) max1544 toc01 load current (a) output voltage (v) 40 50 30 10 20 1.40 1.42 1.44 1.46 1.48 1.50 1.521.38 06 0 100 9080 70 60 50 0.1 1 10 100 efficiency vs. load current (v out = 1.50v) max1544 toc02 load current (a) efficiency (%) v in = 20v v in = 12v v in = 8v skip = refskip = v cc output voltage vs. load current (v out = 1.00v) max1544 toc03 load current (a) output voltage (v) 50 10 30 20 40 0.92 0.94 0.96 0.98 1.00 1.020.90 06 0 100 9080 50 0.1 10 100 7060 load current (a) efficiency (%) 1 efficiency vs. load current (v out = 1.00v) max1544 toc04 v in = 20v v in = 12v v in = 8v skip = refskip = v cc output voltage vs. load current (v out = 0.80v) max1544 toc05 load current (a) output voltage (v) 30 sus = v cc 10 20 0.74 0.76 0.78 0.80 0.820.72 04 0 100 9080 50 0.1 10 100 7060 load current (a) efficiency (%) 1 dual-phase efficiency vs. load current (v out = 0.80v) max1544 toc06 v in = 20v v in = 8v v in = 12v skip = ref 100 9080 50 0.1 10 100 7060 load current (a) efficiency (%) 1 single-phase efficiency vs. load curren t (v out = 0.80v) max1544 toc07 v in = 20v v in = 8v v in = 12v skip = gnd switching frequency vs. load current max1544 toc08 load current (a) switching frequency (khz) 30 10 20 100 200 300 400 0 04 0 v out = 1v (no load) skip mode (skip = ref) forced-pwm (skip = v cc ) no-load supply current vs. input voltage (forced-pwm mode) max1544 toc09 input voltage (v) supply current (ma) 20 25 5 15 10 30 60 90 120 150 0 03 0 i in skip = v cc i cc + i dd typical operating characteristics (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = skip = v cc , d0 d4 set for 1.5v (sus = gnd), s0 s1 set for 1v (sus = v cc ), ofs = gnd, t a = +25 c, unless otherwise specified.) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 10 ______________________________________________________________________________________ no-load supply current vs. input voltage (pulse skipping) max1544 toc10 input voltage (v) supply current (ma) 20 25 5 15 10 0.5 1.0 1.5 2.0 2.5 3.0 0 03 0 i in skip = ref i cc + i dd output offset voltage vs. ofs voltage max1544 toc11 ofs voltage (v) output offset voltage (mv) 1.5 0.5 1.0 -100 -50 0 50 100 150 -150 0 2.0 undefined region reference voltage distribution max1544 toc12 reference voltage (v) sample percentage (%) 2.005 1.995 2.000 10 20 30 40 50 0 1.990 2.010 sample size = 100 current-balance offset voltage distribution max1544 toc13 offset voltage (mv) sample percentage (%) 1.25 -1.25 0 10 20 30 40 50 0 -2.50 2.50 sample size = 100 current-limit threshold distribution max1544 toc14 current limit (mv) sample percentage (%) 10.5 9.5 10.0 10 20 30 40 50 0 9.0 11.0 v ilim = 0.20v sample size = 100 60 -40 0.1 10 100 1k 1 10k voltage-positioning amplifier gain and phase vs. frequency -20 -10 0 -30 max1544 toc15 frequency (hz) gain (db) phase (degrees) 10 20 30 40 50 180 -180 -108 -72 -36 -144 0 36 72 108 144 gain phase vps amplifier offset voltage vs. common-mode voltage max1544 toc16 common-mode voltage (v) 34 1 2 05 offset voltage ( v) 20 40 60 80 100 120 140 160 180 0 vps amplifier disabled inductor current difference vs. load current max1544 toc17 load current (a) 30 40 10 20 05 0 i l(cs) - i l(cm) (a) 0.2 0.4 0.6 0.8 1.0 0 r sense = 1m skip = ref skip = v cc typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = skip = v cc , d0 d4 set for 1.5v (sus = gnd), s0 s1 set for 1v (sus = v cc ), ofs = gnd, t a = +25 c, unless otherwise specified.) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 11 power-up sequence max1544 toc18 5v 0 0 5v 0 2v1v b c a 1ms/div a. shdn, 5v/divb. 1.5v output, 1v/div c. vrok, 5v/div r time = 64.9k soft-start max1544 toc19 5v 00 0 10a 0 1.5v b cd a 100 s/div a. shdn, 5v/divb. 1.5v output, 1v/div c. i l1 , 10a/div d. i l2 , 10a/div r load = 75m , r time = 64.9k soft-shutdown max1544 toc20 5v 10a 0 0 10a 0 1.5v b c d a 200 s/div a. shdn, 5v/divb. 1.5v output, 1v/div c. i l1 , 10a/div d. i l2 , 10a/div r load = 75m , r time = 64.9k 1.50v load transient (10a to 50a load) max1544 toc21 50a 20a 0 0 20a 10a 1.5v b cd a 20 s/div a. load current, (i load = 10a to 50a), 50a/div b. output voltage (1.50v no load), 100mv/divc. i l1 , 10a/div d. i l2 , 10a/div typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = skip = v cc , d0 d4 set for 1.5v (sus = gnd), s0 s1 set for 1v (sus = v cc ), ofs = gnd, t a = +25 c, unless otherwise specified.) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = skip = v cc , d0 d4 set for 1.5v (sus = gnd), s0 s1 set for 1v (sus = v cc ), ofs = gnd, t a = +25 c, unless otherwise specified.) 1.00v load transient (10a to 30a load) max1544 toc22 30a 0 0 10a10a 10a 1.0v b cd a 20 s/div a. load current, (i load = 10a to 30a), 25a/div b. output voltage (1.00v no load), 50mv/divc. i l1 , 10a/div d. i l2 , 10a/div offset transition max1544 toc23 0.2v 5a5a 0 1.5v b cd a 20 s/div a. v ofs = 0 to 200mv, 0.2v/div b. v out = 1.500v to 1.475, 20mv/div c. i l1 , 10a/div d. i l2 , 10a/div 10a load suspend transition (dual-phase pwm operation) max1544 toc24 3.3v 2.5a2.5a 0 1.5v1.0v b cd a 40 s/div a. sus, 5v/divb. v out = 1.5v to 1.0v, 0.5v/div c. i l1 , 10a/div d. i l2 , 10a/div 5a load, skip = v cc , r time = 64.9k suspend transition (single-phase skip operation) max1544 toc25 3.3v 0 10a 0 10a 0 1.5v1.0v b cd a 100 s/div a. sus, 5v/divb. v out = 1.5v to 1.0v, 0.5v/div c. i l1 , 10a/div d. i l2 , 10a/div 5a load, c out = (4) 680 f, skip = sus, r time = 64.9k downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 13 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd = 5v, shdn = skip = v cc , d0 d4 set for 1.5v (sus = gnd), s0 s1 set for 1v (sus = v cc ), ofs = gnd, t a = +25 c, unless otherwise specified.) single-phase skip to dual-phase pwm transition max1544 toc26 5v 00 1.5v b cd a 20 s/div a. skip = v cc to gnd, 5v/div b. 1.5v output, 50mv/divc. i l1 , 10a/div d. i l2 , 10a/div 2a load dual-phase skip to dual-phase pwm transition max1544 toc27 5v2v 00 1.5v b cd a 20 s/div a. skip = v cc to ref, 5v/div b. 1.5v output, 50mv/divc. i l1 , 10a/div d. i l2 , 10a/div 2a load 100mv dac code transition max1544 toc28 3.3v 0 5a5a 1.5v1.4v b cd a 20 s/div a. d1, 5v/divb. v out = 1.50v to 1.40v, 100mv/div c. i l1 , 10a/div d. i l2 , 10a/div 10a load 400mv dac code transition max1544 toc29 3.3v 0 1.5v1.1v b cd a 40 s/div a. d3, 5v/divb. v out = 1.50v to 1.10v, 0.5v/div c. i l1 , 10a/div d. i l2 , 10a/div 10a load 5a5a downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 14 ______________________________________________________________________________________ pin description pin name function 1 time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew-rate clock. a150k to 15k resistor sets the clock from 100khz to 1mhz, f slew = 500khz 30k /r time . 2 ton on-time selection control input. this four-level input sets the k-factor value used to determine thedh_ on-time (see the on-time one-shot (t on ) section): gnd = 550khz, ref = 300khz, open = 200khz, v cc = 100khz 3 sus suspend input. sus is a three-level logic input. when the controller detects on-transition on sus, thecontroller slews the output voltage to the new voltage level determined by sus, s0 s1, and d0 d4. the controller blanks vrok during the transition and another 24 r time clock cycles after the new dac code is reached. connect sus as follows to select which multiplexer sets the nominal outputvoltage: 3.3v or v cc (high) = suspend mode; s0 s1 low-range suspend code (table 5) ref = suspend mode; s0 s1 high-range suspend code (table 5) gnd = normal operation; d0 d4 vid dac code (table 4) 4, 5 s0, s1 suspend-mode voltage select inputs. s0 s1 are four-level digital inputs that select the suspend mode vid code (table 5) for the suspend mode multiplexer inputs. if sus is high, the suspend modevid code is delivered to the dac (see the internal multiplexers section), overriding any other voltage setting (figure 3). 6 shdn s hutd ow n c ontr ol inp ut. thi s i np ut cannot w i thstand the b atter y vol tag e. c onnect to v c c for nor m al op er ati on. c onnect to g r ound to p ut the ic i nto i ts 1a ( typ ) shutd ow n state. d ur i ng the tr ansi ti on fr om nor m al op er ati on to shutd ow n, the outp ut vol tag e r am p s d ow n at 4 ti m es the outp ut- vol tag e sl ew r ate p r og r am m ed b y the tim e p i n. in shutd ow n m od e, d lm and d ls ar e for ced to v d d to cl am p the outp ut to g r ound . for ci ng sh dn to 12v ~ 15v d i sab l es b oth over vol tag e p r otecti on and und er vol tag e p r otecti on ci r cui ts, d i sab l es over l ap op er ati on, and cl ear s the faul t l atch. d o not connect sh dn to > 15v . 7 ofs voltage-divider input for offset control. for 0 < v ofs < 0.8v, 0.125 times the voltage at ofs is subtracted from the output. for 1.2v < v ofs < 2v, 0.125 times the difference between ref and ofs is added to the output. voltages in the range of 0.8v < v ofs < 1.2v are undefined. the controller disables the offset amplifier during suspend mode (sus = ref or high). 8 ref 2v reference output. bypass to gnd with 0.22? or greater ceramic capacitor. the reference cansource 100? for external loads. loading ref degrades output voltage accuracy according to the ref load regulation error. 9 ilim current-limit adjustment. the current-limit threshold defaults to 30mv if ilim is tied to v cc . in adjustable mode, the current-limit threshold voltage is precisely 1/20 the voltage seen at ilim over a0.2v to 1.5v range. the logic threshold for switchover to the 30mv default value is approximately v cc - 1v. 10 v cc analog supply voltage input for pwm core. connect v cc to the system supply voltage (4.5v to 5.5v) with a series 10 resistor. bypass to gnd with a 1? or greater ceramic capacitor, as close to the ic as possible. 11 gnd analog ground. connect the max1544 s exposed pad to analog ground. 12 ccv voltage integrator capacitor connection. connect a 47pf to 1000pf (47pf typ) capacitor from ccvto analog ground (gnd) to set the integration time constant. 13 gnds ground remote-sense input. connect gnds directly to the cpu ground-sense pin. gnds internallyconnects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground. downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 15 pin name function 14 cci current balance compensation. connect a 470pf capacitor between cci and fb. see the current balance compensation section. 15 fb feedback input. fb is internally connected to both the feedback input and the output of the voltage-positioning op amp. see the setting voltage positioning section to set the voltage-positioning gain. 16 oain- op amp inverting input and op amp disable input. when using the internal op amp for additionalvoltage-positioning gain, connect to the negative terminal of current-sense resistor through a resistor as described in the setting voltage positioning section. connect oain- to v cc to disable the op amp. the logic threshold to disable the op amp is approximately v cc - 1v. 17 oain+ op amp noninverting input. when using the internal op amp for additional voltage-positioning gain,connect to the positive terminal of current-sense resistor through a resistor as described in the setting voltage positioning section. 18 skip pulse-skipping select input. when pulse skipping, the controller blanks the vrok upper threshold:3.3v or v cc (high) = dual-phase forced-pwm operation ref = dual-phase pulse-skipping operationgnd = single-phase pulse-skipping operation 19 ovp overvoltage protection enable input. connect ovp to v cc to enable the output overvoltage fault protection. connect ovp to gnd to disable the output overvoltage fault protection. during normal forced-pwm operation ( skip = high), the controller detects an ovp fault if the output voltage exceeds the set dac voltage by more than 13% (min). during pulse-skipping operation ( skip = ref or gnd), the controller detects an ovp fault if the output voltage exceeds the fixed 2v (typ) threshold. if anovervoltage fault occurs, the controller is immediately shutdown and the output is discharged. see the fault protection section. 20 24 d4 d0 low-voltage vid dac code inputs. the d0 d4 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. in normal mode (table 4, sus = gnd), theoutput voltage is set by the vid code indicated by the logic-level voltages on d0-d4. in suspend mode (table 5, sus = ref or high), the decoded state of the four-level s0 s1 inputs sets the output voltage. 25 vrok open-drain power-good output. after output voltage transitions, except during power-up and power-down, if out is in regulation then vrok is high impedance. the controller blanks vrok whenever the slew rate control is active (output voltage transitions). vrok is forced low in shutdown. a pullup resistor on vrok causes additional finite shutdown current. during power-up, vrok includes a 3ms (min) delay after the output reaches the regulation voltage. 26 bstm main boost flying capacitor connection. an optional resistor in series with bstm allows the dhmpullup current to be adjusted. 27 lxm main inductor connection. lxm is the internal lower supply rail for the dhm high-side gate driver. 28 dhm main high-side gate-driver output. swings lxm to bstm. 29 dlm m ai n low - s i d e g ate- d r i ver o utp ut. d lm sw i ng s fr om p gn d to v d d . d lm i s for ced hi g h after the m ax 1544 p ow er s d ow n. 30 v dd supply voltage input for the dlm and dls gate drivers. connect to the system supply voltage (4.5vto 5.5v). bypass v dd to pgnd with a 2.2? or greater ceramic capacitor as close to the ic as possible. 31 pgnd power ground. ground connection for low-side gate drivers dlm and dls. pin description (continued) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 16 ______________________________________________________________________________________ detailed description dual 180 out-of-phase operation the two phases in the max1544 operate 180 out-of- phase ( skip = ref or high) to minimize input and output filtering requirements, reduce electromagnetic interfer-ence (emi), and improve efficiency. this effectively low- ers component count reducing cost, board space, and component power requirements making the max1544 ideal for high-power, cost-sensitive applications.typically, switching regulators provide transfer power using only one phase instead of dividing the power among several phases. in these applications, the input capacitors must support high-instantaneous current requirements. the high-rms ripple current can lower efficiency due to i 2 r power loss associated with the input capacitor s effective series resistance (esr). therefore, the system typically requires several low-esr inputcapacitors in parallel to minimize input voltage ripple, to reduce esr-related power losses, and to meet the necessary rms ripple current rating. with the max1544, the controller shares the current between two phases that operate 180 out-of-phase, so the high-side mosfets never turn on simultaneouslyduring normal operation. the instantaneous input cur- rent of either phase is effectively cut in half, resulting in reduced input voltage ripple, esr power loss, and rmsripple current (see the input capacitor selection sec- tion). as a result, the same performance can beachieved with fewer or less-expensive input capacitors. table 1 lists component selection for standard multi- phase selections and table 2 is a list of component suppliers. transient overlap operation when a transient occurs, the response time of the con-troller depends on how quickly it can slew the inductor current. multiphase controllers that remain 180 degrees out-of-phase when a transient occurs actually respond slower than an equivalent single-phase controller. in order to provide fast transient response, the max1544 supports a phase-overlap mode, which allows the dual regulators to operate in-phase when heavy-load tran- sients are detected, reducing the response time. after either high-side mosfet turns off, if the output voltage does not exceed the regulation voltage when the mini- mum off-time expires, the controller simultaneously turns on both high-side mosfets during the next on- time cycle. this maximizes the total inductor current slew rate. the phases remain overlapped until the out- put voltage exceeds the regulation voltage after the minimum off-time expires. pin description (continued) pin name function 32 dls s econd ar y low - s i d e g ate- d r i ver o utp ut. d ls sw i ng s fr om p gn d to v d d . d ls i s for ced hi g h after the m ax 1544 p ow er s d ow n. 33 dhs secondary high-side gate-driver output. swings lxs to bsts. 34 lxs secondary inductor connection. lxs is the internal lower supply rail for the dhs high-side gatedriver. 35 bsts secondary boost flying capacitor connection. an optional resistor in series with bsts allows thedhs pullup current to be adjusted. 36 v+ battery voltage-sense connection. used only for pwm one-shot timing. dh_ on-time is inverselyproportional to input voltage over a range of 4v to 28v. 37 cmp main inductor positive current-sense input 38 cmn main inductor negative current-sense input 39 csn secondary inductor positive current-sense input 40 csp secondary inductor negative current-sense input downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 17 after the phase-overlap mode ends, the controller auto-matically begins with the opposite phase. for example, if the secondary phase provided the last on-time pulse before overlap operation began, the controller starts switching with the main phase when overlap operation ends. power-up sequence the max1544 is enabled when shdn is driven high (figure 2). the reference powers up first. once the ref-erence exceeds its uvlo threshold, the pwm controller evaluates the dac target and starts switching. for the max1544, the slew-rate controller ramps up theoutput voltage in 25mv increments to the proper operat- ing voltage (see tables 3 and 4) set by either d0 d4 (sus = gnd) or s0 s1 (sus = ref or high). the ramp rate is set with the r time resistor (see the output voltage transition timing section). the ramp rate is set with the r time resistor (see the output voltage transition timing section). the con- troller pulls vrok low until at least 3ms after themax1544 reaches the target dac code. max1544 amd mobile components max1544 amd desktop components designation circuit of figure 1 circuit of figure 12 input voltage range 7v to 24v 7v to 24v vid output voltage(d4 d0) 1.5v (d4 d0 = 00010) 1.5v (d4 d0 = 00010) suspend voltage(sus, s0 s1) not used (sus = gnd) not used (sus = gnd) maximum load current 60a 70a number of phases ( total ) two phases (1) max1544 four phases (1) max1544 + (2) max1980 inductor (per phase) 0.6? panasonic etqp1h0r6bfa 0.7? panasonic etqp2h0r7bfa or 0.8? sumida cdep105l-0r8 switching frequency 300khz (ton = ref) 300khz (ton = ref) high-side mosfet(n h , per phase) siliconix (1) si7886dp or international rectifier (2) irf6604 international rectifier (1) irf7811w or fairchild (1) fds6694 low-side mosfet(n l , per phase) siliconix (2) si7442dp or international rectifier (2) irf6603 fairchild (2) fds6688 or siliconix (1) si7442dp total input capacitance (c in ) (8) 10?, 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m (8) 10?, 25v taiyo yuden tmk432bj106km or tdk c4532x5r1e106m total output capacitance(c out ) (4) 680?, 2.5v sanyo 2r5tpd680m (5) 680?, 2.5v sanyo 2r5tpd680m current-sense resistor(r sense , per phase) 1m panasonic erjm1wtj1m0u 1m panasonic erjm1wtj1m0u table 1. component selection for standard multiphase applications downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 18 ______________________________________________________________________________________ input*7v to 24v output v cc vrokshdn ofs power good off on d0 dac inputs suspend inputs (four-level logic) l1 c bst1 0.22 f n h1 n h2 n l1 c in c2 1 f c ref 0.22 f r13 10 r12 100k c ccv 47pf c cci 470pfc bst2 0.22 f r7158k 1% c3 100pf r10 1.5k 1% r11.5k 1% 5v bias supply c12.2 f c out c out *lower input voltages require additional input capacitance. bstdiodes ovpsus timeccv skip r sense1 1.0m n l2 r630.1k 1% r8 100k 1% r4 1k 1% r51k 1% power groundanalog ground max1544 c in ref ton ref v cc (ovp enabled) r2 1k 1% r31k 1% r time 64.9k d1 d2 d3 d4 s0 s1 l2 r sense2 1.0m bstm dhm lxm dlm pgnd gnd cmn cmp v+ oain+ oain- ref (300khz) fb cci csp csn bsts dhs lxs dls gnds v dd ilim r9 49.9k 1% skip pwm figure 1. standard two-phase amd mobile 60a application circuit downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 19 shutdown when shdn goes low, the max1544 enters low-power shutdown mode. vrok is pulled low immediately, andthe output voltage ramps down to 0v in lsb increments at 4 times the clock rate set by r time : where f slew = 500khz ? 30k /r time , v dac is the dac setting when the controller begins the shutdownsequence, and v lsb = 25mv is the dac s smallest volt- age increment. slowly discharging the output capacitorsby slewing the output over a long period of time (4/f slew ) keeps the average negative inductor current low (damped response), thereby eliminating the nega-tive output voltage excursion that occurs when the con- troller discharges the output quickly by permanently turning on the low-side mosfet (underdamped response). t f v v shdn slew dac lsb ?? ? ?? ? 4 manufacturer phone website bi technologies 714-447-2345 (usa) www.bitechnologies.com central semiconductor 631-435-1110 (usa) www.centralsemi.com coilcraft 800-322-2645 (usa) www.coilcraft.com coiltronics 561-752-5000 (usa) www.coiltronics.com fairchild semiconductor 888-522-5372 (usa) www.fairchildsemi.com international rectifier 310-322-3331 (usa) www.irf.com kemet 408-986-0424 (usa) www.kemet.com panasonic 847-468-5624 (usa) www.panasonic.com sanyo 65-6281-3226 (singapore) www.secc.co.jp siliconix (vishay) 203-268-6261 (usa) www.vishay.com sumida 408-982-9660 (usa) www.sumida.com taiyo yuden 03-3667-3408 (japan) 408-573-4150 (usa) www.t-yuden.com tdk 847-803-6100 (usa) 81-3-5201-7241 (japan) www.component.tdk.com toko 858-675-8013 (usa) www.tokoam.com table 2. component suppliers vid (d0?4) shdn v core t vrok(start) 3ms (typ) soft-shutdown 1 lsb per 4 r time cycles soft-start 1 lsb per r time cycle vrok do not care figure 2. power-up and shutdown sequence timing diagram downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 20 ______________________________________________________________________________________ this eliminates the need for the schottky diode normallyconnected between the output and ground to clamp the negative output voltage excursion. when the dac reaches the 0v setting, dl_ goes high, dh_ goes low, the reference turns off, and the supply current drops to about 1?. when a fault condition output undervoltage lockout, output overvoltage lockout (ovp = v cc ), or ther- mal shutdown activates the shutdown sequence, the controller sets the fault latch to prevent the controller fromrestarting. to clear the fault latch and reactivate the con- troller, toggle shdn or cycle v cc power below 1v. when shdn goes high, the reference powers up. once the reference voltage exceeds its uvlo threshold, thecontroller evaluates the dac target and starts switching. the slew-rate controller ramps up from 0v in lsb increments to the currently selected output-voltage set- ting (see the power-up sequence section). there is no traditional soft-start (variable current-limit) circuitry, sofull output current is available immediately. internal multiplexers the max1544 has a unique internal dac input multiplexer (muxes) that selects one of three different dac code settings for different processor states (figure 3). on startup, the max1544 selects the dac code from the d0 d4 (sus = gnd) or s0 s1 (sus = ref or high) input decoders. dac inputs (d0?4) during normal forced-pwm operation (sus = gnd), thedigital-to-analog converter (dac) programs the output voltage using the d0 d4 inputs. do not leave d0 d4 unconnected. d0 d4 can be changed while the max1544 is active, initiating a transition to a new outputvoltage level. change d0 d4 together, avoiding greater than 1? skew between bits. otherwise, incor-rect dac readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall tran- sition time. the available dac codes and resulting out- put voltages are compatible with amd hammer voltage specifications (table 4). four-level logic inputs ton and s0 s1 are four-level logic inputs. these inputs help expand the functionality of the controllerwithout adding an excessive number of pins. the four- level inputs are intended to be static inputs. when left open, an internal resistive voltage-divider sets the input voltage to approximately 3.5v. therefore, connect the four-level logic inputs directly to v cc , ref, or gnd when selecting one of the other logic levels. see the electrical characteristics for exact logic level voltages. shdn sus skip ofs output voltage operating mode gnd x x x gnd low-power shutdown mode. dl_ is forced high, dh_ isforced low, and the pwm controller is disabled. the supply current drops to 1? (typ). v cc gnd v cc gnd or ref d0 d4 (no offset) n or m al op er ati on. the no- l oad outp ut vol tag e i s d eter m i ned b y the sel ected v id d ac cod e ( d 0 d 4, tab l e 4) . v cc x gnd or ref gnd or ref d0 d4 (no offset) pulse-skipping operation. when skip is pulled low, the max1544 immediately enters pulse-skipping operationallowing automatic pwm/pfm switchover under light loads. the vrok upper threshold is blanked. v cc gnd x 0 to 0.8v or 1.2v to 2v d0 d4 (plus offset) deep-sleep mode. the no-load output voltage is determinedby the selected vid dac code (d0 d4, table 4) plus the offset voltage set by ofs. v cc ref or high xx sus, s0 s1 (no offset) suspend mode. the no-load output voltage is determined bythe selected suspend code (sus, s0 s1, table 5), overriding all other active modes of operation. v cc x x x gnd fault mode. the fault latch has been set by either uvp, ovp,or thermal shutdown. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. operating mode truth table downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 21 suspend mode when the processor enters low-power suspend mode, itsets the regulator to a lower output voltage to reduce power consumption. the max1544 includes independent suspend-mode output voltage codes set by the four-level s0 s1 inputs and the three-level sus input. when the cpu suspends operation (sus = ref or high), the con-troller disables the offset amplifier and overrides the 5-bit vid dac code set by either d0 d4 (normal operation). the master controller slews the output to the selectedsuspend-mode voltage. during the transition, the max1544 blanks vrok and the uvp fault protection until 24 r time clock cycles after the slew-rate controller reach- es the suspend-mode voltage.sus is a three-level logic input: gnd, ref, or high. this expands the functionality of the controller without adding an additional pin. this input is intended to be driven by a dedicated open-drain output with the pullup resistor connected either to ref (or a resistive divider from v cc ) or to a logic-level bias supply (3.3v or greater). when pulled up to ref, the max1544 selectsthe upper suspend voltage range. when pulled high (2.7v or greater), the controller selects the lower sus- pend voltage range. see the electrical characteristics for exact logic level voltages. output voltage transition timing the max1544 is designed to perform mode transitions ina controlled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest pos- sible peak currents for a given output capacitance. at the beginning of an output voltage transition, the max1544 blanks the vrok output, preventing it from changing states. vrok remains blanked during the transition and is enabled 24 clock cycles after the slew-rate controller has set the final dac code value. the slew-rate clock frequency (set by resistor r time ) must be set fast enough to ensure that the transition iscompleted within the maximum allotted time. the slew-rate controller transitions the output voltage in 25mv steps during soft-start, soft-shutdown, and sus- pend-mode transitions. the total time for a transition depends on r time , the voltage difference, and the accuracy of the max1544 s slew-rate clock, and is not dependent on the total output capacitance. the greaterthe output capacitance, the higher the surge current required for the transition. the max1544 automatically controls the current to the minimum level required to complete the transition in the calculated time, as long s0s1 s0?1 decoder in sel sus suspend mux out 1 0 sel dac 1.0v 2.5v sus 3-leveldecoder out d0?4 decoder in out d3d4 d1d2 d0 figure 3. internal multiplexers functional diagram downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 22 ______________________________________________________________________________________ as the surge current is less than the current limit set byilim. the transition time is given by: where f slew = 500khz ? 30k / r time , v old is the original dac setting, v new is the new dac setting, and v lsb = 25mv is the dac s smallest voltage increment. the additional two clock cycles on the falling edge timeare due to internal synchronization delays. see time frequency accuracy in the electrical characteristics for f slew limits. the practical range of r time is 15k to 150k , corre- sponding to 1.0? to 10? per 25mv step. although thedac takes discrete steps, the output filter makes the transitions relatively smooth. the average inductor cur- rent required to make an output voltage transition is: fault protection output overvoltage protection the max1544 features selectable output ovp. connectovp to v cc to enable the output overvoltage-fault pro- tection. the ovp circuit is designed to protect the cpuagainst a shorted high-side mosfet by drawing high current and blowing the battery fuse. the max1544 continuously monitors the output for an overvoltage fault. during normal forced-pwm operation ( skip = high), the controller detects an ovp fault if the outputvoltage exceeds the set dac voltage by more than 13% (min). during pulse-skipping operation ( skip = ref or gnd), the controller detects an ovp fault if the outputvoltage exceeds the fixed 2.0v (typ) threshold. when the ovp circuit detects an overvoltage fault, it immedi- ately sets the fault latch and activates the shutdown sequence. this action discharges the output filter capacitor and forces the output to ground. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 1v. to disable the overvoltage protection, connect ovp tognd. the ovp is also disabled when the controller is in the no-fault test mode (see the no-fault test mode section). ic v f l out lsb slew ? t f vv v for v ri g t f vv v for v falling slew slew old new lsb out slew slew old new lsb out ?? ? ?? ? ?? ? ?? ? + ?? ?? ?? ?? ? ? 11 2 sin sus v dac time clock vrok vrok blanking vrok blanking output set by sus and s0-s1 output set by d0?4 1 lsb per r time cycle t slew t blank = 24 clks t slew t blank = 24 clks figure 4. suspend transition downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 23 output undervoltage shutdown the output uvp function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the max1544 output voltage is under 70% of the nominal value, the controller activates the shutdown sequence and sets the fault latch. once the controller ramps down to the 0v dac code setting, it forces the dl_ low-side gate driver high and pulls the dh_ high-side gate driver low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the controller. uvp is ignoredduring output voltage transitions and remains blanked for an additional 24 clock cycles after the controller reaches the final dac code value. uvp can be disabled through the no-fault test mode (see the no-fault test mode section). thermal-fault protection the max1544 features a thermal-fault protection circuit.when the junction temperature rises above +160 c, a thermal sensor activates the fault latch and the soft-shutdown sequence. once the controller ramps down to the 0v dac code setting, it forces the dl_ low-side gate driver high, and pulls the dh_ high-side gate driver low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the con-troller after the junction temperature cools by 15 c. thermal shutdown can be disabled through theno-fault test mode (see the no-fault test mode section). no-fault test mode the latched-fault protection features and overlap modecan complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a no- fault test mode is provided to disable the fault protection (overvoltage protection, undervoltage protection, and thermal shutdown) and overlap mode. additionally, the test mode clears the fault latch if it has been set. the no- fault test mode is entered by forcing 12v to 15v on shdn . multiphase quick-pwm 5v bias supply (v cc and v dd ) the quick-pwm controller requires an external 5v biassupply in addition to the battery. typically, this 5v bias supply is the notebook s 95%-efficient 5v system sup- ply. keeping the bias supply external to the icimproves efficiency and eliminates the cost associated with the 5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the 5v bias supply can be generated with an external linear regulator. the 5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: i bias = i cc + f sw (q g(low) + q g(high) ) d4 d3 d2 d1 d0 output voltage (v) 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 d4 d3 d2 d1 d0 output voltage (v) 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 shutdown table 4. output voltage vid dac codes (sus = gnd) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 24 ______________________________________________________________________________________ csncsp cmp cmn v cc refgnd ccv ofs fb oain+ oain- gnds 1.0v time ilim 19r r ref (2.0v) shdn ref t = 1 t t = 0 gm gm r-2r dac internal multiplexers, mode control, and slew-rate control s[0:1] d[0:4] sus skip q q t cmp cmn skip fault 1.5mv s r q r s q on-time one-shot trig q on-time one-shot trig q bstm ton v+ cci dhm lxm v dd dlm pgnd main phase drivers trig q one-shot minimum off-time secondary phase drivers fb gm gm cmpcsp cmn csn bsts dhs lxs dls gm max1544 figure 5. dual-phase quick-pwm functional diagram downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 25 lower suspend codes sus* s1 s0 output voltage (v) high gnd gnd 0.675 high gnd ref 0.700 high gnd open 0.725 high gnd v cc 0.750 high ref gnd 0.775 high ref ref 0.800 high ref open 0.825 high ref v cc 0.850 high open gnd 0.875 high open ref 0.900 high open open 0.925 high open v cc 0.950 high v cc gnd 0.975 high v cc ref 1.000 high v cc open 1.025 high v cc v cc 1.050 upper suspend codes sus* s1 s0 output voltage (v) ref gnd gnd 1.075 ref gnd ref 1.100 ref gnd open 1.125 ref gnd v cc 1.150 ref ref gnd 1.175 ref ref ref 1.200 ref ref open 1.225 ref ref v cc 1.250 ref open gnd 1.275 ref open ref 1.300 ref open open 1.325 ref open v cc 1.350 ref v cc gnd 1.375 ref v cc ref 1.400 ref v cc open 1.425 ref v cc v cc 1.450 table 5. suspend mode dac codes* connect the three-level sus input to a 2.7v or greater supply (3.3v or v cc ) for an input logic level high. where i cc is provided in the electrical characteristics , f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheet s total gate-charge specification limits at v gs = 5v. v+ and v dd can be tied together if the input power source is a fixed 4.5v to 5.5v supply. if the 5v biassupply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensurestartup. free-running, constant-on-time pwm controller with input feed forward the quick-pwm control architecture is a pseudofixed-frequency, constant-on-time, current-mode regulator with input voltage feed forward (figure 5). this architecture relies on the output filter capacitor s esr to act as the current-sense resistor, so the output ripple voltage pro-vides the pwm ramp signal. the control algorithm is sim- ple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to output voltage or the difference between the main and secondary inductor currents (see the on-time one-shot ( ton ) section). another one-shot sets a minimum off-time. the on-timeone-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current-limit threshold, and the minimum off-time one-shot times out. the controller maintains 180 out-of- phase operation by alternately triggering the main andsecondary phases after the error comparator drops below the output voltage set point. on-time one-shot (ton) the core of each phase contains a fast, low-jitter,adjustable one-shot that sets the high-side mosfets on-time. the one-shot for the main phase varies the on- time in response to the input and feedback voltages. the main high-side switch on-time is inversely propor- tional to the input voltage as measured by the v+ input, and proportional to the feedback voltage (v fb ): where k is set by the ton pin-strap connection (table 6)and 0.075v is an approximation to accommodate the expected drop across the low-side mosfet switch. t on main kv v v fb in () . = + () 0 075 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 26 ______________________________________________________________________________________ the one-shot for the secondary phase varies the on-timein response to the input voltage and the difference between the main and secondary inductor currents. two identical transconductance amplifiers integrate the difference between the master and slave current-sense signals. the summed output is internally connected to cci, allowing adjustment of the integration time constant with a compensation network connected between cci and fb. the resulting compensation current and voltage are determined by the following equations: where z cci is the impedance at the cci output. the secondary on-time one-shot uses this integrated signal(v cci ) to set the secondary high-side mosfets on-time. when the main and secondary current-sense signals(v cm = v cmp - v cmn and v cs = v csp - v csm ) become unbalanced, the transconductance amplifiers adjust thesecondary on-time, which increases or decreases the secondary inductor current until the current-sense signals are properly balanced: this algorithm results in a nearly constant switching frequency and balanced inductor currents, despite the lack of a fixed-frequency clock generator. the benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions such as the 455khz if band; second, the induc- tor ripple-current operating point remains relatively con- stant, resulting in easy design methodology and predictable output-voltage ripple. the on-time one-shots have good accuracy at the operating points specified in the electrical characteristics . on-times at operating points far removed from the conditions specified in the electrical characteristics can vary over a wider range. for example, the 300khz setting typically runs about 3%slower with inputs much greater than 12v due to the very short on-times required. on-times translate only roughly to switching frequencies. the on-times guaranteed in the electrical characteristics are influenced by switching delays in the external high-side mosfet. resistive losses, including the inductor, both mosfets, output capacitor esr, and pc boardcopper losses in the output and ground tend to raise the switching frequency at higher output currents. also, the dead-time effect increases the effective on-time, reduc- ing the switching frequency. it occurs only during forced- pwm operation and dynamic output voltage transitions when the inductor current reverses at light or negative load currents. with reversed inductor current, the induc- tor s emf causes lx to go high earlier than normal, extending the on-time by a period equal to the dh-risingdead time. for loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency (per phase) is: where v drop1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous recti-fier, inductor, and pc board resistances; v drop2 is the sum of the parasitic voltage drops in the inductor chargepath, including high-side switch, inductor, and pc board resistances; and t on is the on-time as determined above. current balance without active current-balance circuitry, the currentmatching between phases depends on the mosfet s on-resistance (r ds(on) ), thermal ballasting, on-/off-time matching, and inductance matching. for example, vari-ation in the low-side mosfet on-resistance (ignoring thermal effects) results in a current mismatch that is proportional to the on-resistance difference: however, mismatches between on-times, off-times, and inductor values increase the worst-case current imbal- ance, making it impossible to passively guarantee accurate current balancing. ii i r r main nd main main nd -- 2 2 1 = ?? ? ?? ? ?? ?? ?? ?? f sw vv tv v v out drop on in drop drop = + () + () 1 12 - . . ( ) ( ) () tk vv v k vv v k iz v main on time secondary current balance correction on nd cci in fb in cci cci in 2 0 075 0 075 = + ?? ? ?? ? = + ?? ? ?? ? + ?? ? ?? ? =+ ? ig vvg vv vviz cci m cmp cmn m csp csn cci fb cci cci = () () = + -- - table 6. approximate k-factor errors ton connection frequency setting (khz) k-factor (?) max k-factor error (%) v cc 100 10 ?0 float 200 5 ?0 ref 300 3.3 ?0 gnd 550 1.8 ?2.5 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 27 the multiphase quick-pwm controller integrates thedifference between the current-sense voltages and adjusts the on-time of the secondary phase to maintain current balance. the current balance now relies on the accuracy of the current-sense resistors instead of the inaccurate, thermally sensitive on-resistance of the low- side mosfets. with active current balancing, the current mismatch is determined by the current-sense resistor values and the offset voltage of the transconductance amplifiers: where v os(ibal) is the current balance offset specifica- tion in the electrical characteristics . the worst-case current mismatch occurs immediatelyafter a load transient due to inductor value mismatches resulting in different di/dt for the two phases. the time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. feedback adjustment amplifiers voltage-positioning amplifier the multiphase quick-pwm controllers include an inde-pendent operational amplifier for adding gain to the volt- age-positioning sense path. the voltage-positioning gain allows the use of low-value current-sense resistors in order to minimize power dissipation. this 3mhz gain- bandwidth amplifier was designed with low offset volt- age (70? typ) to meet the imvp output accuracy requirements. the inverting (oain-) and noninverting (oain+) inputs are used to differentially sense the voltage across the voltage-positioning sense resistor. the op amp s output is internally connected to the regulator s feedback input (fb). the op amp should be configured as a noninvert-ing, differential amplifier, as shown in figure 10. the voltage-positioning slope is set by properly selecting the feedback resistor connected from fb to oain- (see the setting voltage positioning section). for applications using a slave controller, additional differential input resistors (summing configuration) can be connected to the slave s voltage-positioning sense resistor. summing together both the master and slave current-sense signalsensures that the voltage-positioning slope remains con- stant when the slave controller is disabled. the controller also uses the amplifier for remote outputsensing (fbs) by summing in the remote-sense voltage into the positive terminal of the voltage-positioning amplifier (figure 10). in applications that do not require voltage-positioning gain, the amplifier can be disabled by connecting the oain- pin directly to v cc . the disabled amplifier s out- put becomes a high impedance, guaranteeing that theunused amplifier does not corrupt the fb input signal. the logic threshold to disable the op amp is approxi- mately v cc - 1v. integrator amplifier a feedback amplifier forces the dc average of thefeedback voltage to equal the vid dac setting. this transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (figure 5), allowing accurate dc output voltage regulation regardless of the output ripple voltage. the feedback amplifier has the ability to shift the output voltage. the differential input voltage range is at least ?0mv total, including dc offset and ac ripple. the integration time constant can be set easily with an external compensation capacitor at the ccv pin. use a capacitor value of 47pf to 1000pf (47pf typ). differential remote sense the multiphase quick-pwm controllers include differen-tial remote-sense inputs to eliminate the effects of volt- age drops down the pc board traces and through the processor s power pins. the remote output sense (fbs) is accomplished by summing in the remote-sense volt-age into the positive terminal of the voltage-positioning amplifier (figure 10). the controller includes a dedicat- ed input and internal amplifier for the remote ground sense. the gnds amplifier adds an offset directly to the feedback voltage, adjusting the output voltage to counteract the voltage drop in the ground path. together, the feedback sense resistor (r fbs ) and gnds input sum the remote-sense voltages with thefeedback signals that set the voltage-positioned output, enabling true differential remote sense of the processor voltage. connect the feedback sense resistor (r fbs ) and ground sense input (gnds) directly to the proces-sor s core supply remote-sense outputs as shown in the standard applications circuit . ii i v r os ibal lm ls os ibal sense () () == - downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 28 ______________________________________________________________________________________ offset amplifier the multiphase quick-pwm controllers include a thirdamplifier used to add small offsets to the voltage-posi- tioned load line. the offset amplifier is summed directly with the feedback voltage, making the offset gain inde- pendent of the dac code. this amplifier has the ability to offset the output by ?00mv. the offset is adjusted using resistive voltage-dividers at the ofs input. for inputs from 0 to 0.8v, the offset amplifier adds a negative offset to the output that is equal to 1/8 the voltage appearing at the selected ofs input (v out = v dac - 0.125 v ofs ). for inputs from 1.2v to 2v, the offset amplifier adds a positive offset tothe output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the selected ofs input (v out = v dac + 0.125 (v ref - v ofs )). with this scheme, the controller supports both positive and negative offsets with a single input. thepiecewise linear transfer function is shown in the typical operating characteristics . the regions of the transfer function below zero, above 2v, and between0.8v and 1.2v are undefined. ofs inputs are disal- lowed in these regions, and the respective effects on the output are not specified. the controller disables the offset amplifier during sus- pend mode (sus = ref or high). forced-pwm operation (normal mode) during normal mode, when the cpu is actively running( skip = high, table 7), the quick-pwm controller oper- ates with the low-noise forced-pwm control scheme.forced-pwm operation disables the zero-crossing comparator, forcing the low-side gate-drive waveform to be constantly the complement of the high-side gate- drive waveform. this keeps the switching frequency fairly constant and allows the inductor current to reverse under light loads, providing fast, accurate neg-ative output voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load 5v bias supply current remains between 10ma to 60ma per phase, depending on the external mosfets and switching frequency. to maintain high efficiency under light-load conditions, the processor may switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. low-power pulse skipping during pulse-skipping override mode ( skip = ref or gnd, table 7), the multiphase quick-pwm controllersuse an automatic pulse-skipping control scheme. when skip is pulled low, the controller uses the automatic pulse-skipping control scheme, overriding forced-pwmoperation, and blanks the upper vrok threshold. table 7. s s k k i i p p settings* skip connection mode operation high (3.3v or v cc ) two-phase forced pwm the controller operates with a constant switching frequency, providing low-noise forced-pwmoperation. the controller disables the zero-crossing comparators, forcing the low-side gate- drive waveform to be constantly the complement of the high-side gate-drive waveform. ref two-phase pulse skipping the controller automatically switches over to pfm operation under light loads. the controllerkeeps both phases active and uses the automatic pulse-skipping control scheme, alternating between the primary and secondary phases with each cycle. gnd one-phase pulse skipping the controller automatically switches over to pfm operation under light loads. only the mainphase is active. the secondary phase is disabled, dls and dhs are pulled low, so lxs is a high impedance. *settings for a dual 180 out-of-phase controller. -200 -100 0 100 200 0 1.0 0.5 0.8 1.2 1.5 2.0 ofs voltage (v) output offset voltage (mv) undefinedregion figure 6. offset voltage downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 29 skip is a three-level logic input gnd, ref, or high. this input is intended to be driven by a dedicatedopen-drain output with the pullup resistor connected either to ref (or a resistive divider from v cc ) or to a logic-level high-bias supply (3.3v or greater). when driven to gnd, the multiphase quick-pwm con- troller disables the secondary phase (dls = pgnd and dhs = lxs) and the primary phase uses the automatic pulse-skipping control scheme. when pulled up to ref, the controller keeps both phases active and uses the automatic pulse-skipping control scheme alternating between the primary and secondary phases with eachcycle. automatic pulse-skipping switchover in skip mode ( skip = ref or gnd), an inherent automatic switchover to pfm takes place at light loads (figure 7). acomparator that truncates the low-side switch on-time at the inductor current s zero crossing affects this switchover. the zero-crossing comparator senses theinductor current across the current-sense resistors. once v c _ p - v c _ n drops below the zero crossing comparator threshold (see the electrical characteristics ), the com- parator forces dl low (figure 5). this mechanism causesthe threshold between pulse-skipping pfm and nonskip- ping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. the pfm/pwm crossover occurs when the load current of each phase is equal to 1/2 the peak-to- peak ripple current, which is a function of the inductor value (figure 7). for a battery input range of 7v to 20v, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: where total is the number of active phases, and k is the on-time scale factor (table 6).the switching waveforms may appear noisy and asyn- chronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. varying the inductor value makes trade-offs between pfm noise and light-load efficiency. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input voltage levels. current-limit circuit the current-limit circuit employs a unique valley cur- rent-sensing algorithm that uses current-sense resistorsbetween the current-sense inputs (c_p to c_n) as the current-sensing elements. if the current-sense signal of the selected phase is above the current-limit threshold, the pwm controller does not initiate a new cycle (figure 8) until the inductor current of the selected phase drops below the valley current-limit threshold. when either phase trips the current limit, both phases are effectively current limited since the interleaved con- troller does not initiate a cycle with either phase. i k load skip total () = ?? ? ?? ? ?? ? ?? ? v l v-v v out in out in inductor current i load = i peak /2 on-time 0 time i peak l v batt - v out ? i ? t = figure 7. pulse-skipping/discontinuous crossover point inductor current i limit(valley) = i load(max) 2 - lir 2 () time 0 i peak i load i limit figure 8. valley current-limit threshold point downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 30 ______________________________________________________________________________________ since only the valley current is actively limited, theactual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. when combined with the undervoltage protec- tion circuit, this current-limit method is effective in almost every circumstance. there is also a negative current limit that prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold isset to approximately 120% of the positive current limit, and therefore tracks the positive current limit when ilim is adjusted. when a phase drops below the negative current limit, the controller immediately activates an on- time pulse dl turns off, and dh turns on allowing the inductor current to remain above the negative cur-rent threshold. the current-limit threshold is adjusted with an external resistive voltage-divider at ilim. the current-limit threshold voltage adjustment range is from 10mv to 75mv. in the adjustable mode, the current-limit thresh- old voltage is precisely 1/20 the voltage seen at ilim. the threshold defaults to 30mv when ilim is connected to v cc . the logic threshold for switchover to the 30mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines toensure that noise and dc errors do not corrupt the cur- rent-sense signals seen by the current-sense inputs (c_p, c_n). mosfet gate drivers (dh, dl) the dh and dl drivers are optimized for driving mod-erately sized, high-side and larger, low-side power mosfets. this is consistent with the low-duty factor seen in the notebook cpu environment, where a large v in - v out differential exists. an adaptive dead-time circuit monitors the dl output and prevents the high-side fet from turning on until dl is fully off. there must be a low-resistance, low-inductance path from the dl driver to the mosfet gate in order for the adaptive dead-time circuit to work properly. otherwise, the sense circuitry in the quick-pwm controller interprets the mosfet gate as off while there is actually charge still left on the gate. use very short, wide traces (50 milsto 100 mils wide if the mosfet is 1in from the device). the dead time at the other edge (dh turning off) is determined by a fixed 35ns internal delay. the internal pulldown transistor that drives dl low is robust, with a 0.4 (typ) on-resistance. this helps pre- vent dl from being pulled up due to capacitive cou- pling from the drain to the gate of the low-sidemosfets when lx switches from ground to v in . applications with high input voltages and long, induc-tive dl traces may require additional gate-to-source capacitance to ensure fast-rising lx edges do not pull up the low-side mosfet s gate voltage, causing shoot- through currents. the capacitive coupling between lxand dl created by the mosfet s gate-to-drain capaci- tance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the minimum threshold voltage:lot-to-lot variation of the threshold voltage can cause problems in marginal designs. typically, adding 4700pf between dl and power ground (c nl in figure 9), close to the low-side mosfets, greatlyreduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. alternatively, shoot-through currents may be caused by a combination of fast high-side mosfets and slow low- side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 in series with bst slows down the high-side mosfet turn-on time, elimi-nating the shoot-through currents without degrading the turn-off time (r bst in figure 9). slowing down the high-side mosfet also reduces the lx node rise time,thereby reducing emi and high-frequency coupling responsible for switching noise. vv c c gs th in rss iss () < ?? ? ?? ? v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input(v in ) n h l v dd dl pgnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching node rise time. (cnl)* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. figure 9. optional gate-driver circuitry downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 31 power-on reset power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch, activatingboot mode, and preparing the pwm for operation. v cc undervoltage lockout (uvlo) circuitry inhibits switch-ing, and forces the dl gate driver high (to enforce out- put overvoltage protection). when v cc rises above 4.25v, the dac inputs are sampled and the output volt-age begins to slew to the target voltage. for automatic startup, the battery voltage should be present before v cc . if the quick-pwm controller attempts to bring the output into regulation without thebattery voltage present, the fault latch trips. toggle the shdn pin to reset the fault latch. input undervoltage lockout during startup, the v cc uvlo circuitry forces the dl gate driver high and the dh gate driver low, inhibitingswitching until an adequate supply voltage is reached. once v cc rises above 4.25v, valid transitions detected at the trigger input initiate a corresponding on-timepulse (see the on-time one-shot (ton) section). if the v cc voltage drops below 4.25v, it is assumed that there is not enough supply voltage to make valid deci-sions. to protect the output from overvoltage faults, the controller activates the shutdown sequence. multiphase quick-pwm design procedure firmly establish the input voltage range and maximumload current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after dropsdue to connectors, fuses, and battery selector switches. if there is a choice at all, lower input volt- ages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil-tering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors,mosfets, and other critical heat-contributing com- ponents. modern notebook cpus generally exhibiti load = i load(max) 80%. for multiphase systems, each phase supports afraction of the load, depending on the current bal- ancing. when properly balanced, the load current is evenly distributed among each phase: where total is the total number of active phases. switching frequency: this choice determines the basic trade-off between size and efficiency. theoptimal frequency is largely a function of maximum input voltage due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapidimprovements in mosfet technology that are mak- ing higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transientresponse vs. output noise. low-inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher out- put noise due to increased ripple current. the mini- mum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction benefit. the optimum operating point is usually found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripplecurrent or lir) determine the inductor value as follows: where total is the total number of phases. find a low-loss inductor having the lowest possible dcresistance that fits in the allotted dimensions. ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): i i lir peak load max total = ?? ? ?? ? + ?? ? ?? ? () 1 2 l vv f i lir v v total in out sw load max out in () = ? ?? ? ?? ? ?? ? ?? ? i i load phase load total () = downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 32 ______________________________________________________________________________________ transient response the inductor ripple current impacts transient-responseperformance, especially at low v in - v out differentials. low inductor values allow the inductor current to slewfaster, replenishing charge removed from the output filter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. for a dual-phase controller, the worst-case output sag voltage can be determined by: where t off(min) is the minimum off-time (see the electrical characteristics ) and k is from table 6. the amount of overshoot due to stored inductor energycan be calculated as: where total is the total number of active phases. setting the current limit the minimum current-limit threshold must be highenough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore:where total is the total number of active phases, and i limit(low) equals the minimum current-limit threshold voltage divided by the current-sense resistor (r sense ). for the 30mv default setting, the minimum current-limitthreshold is 28mv. connect ilim to v cc for the default current-limit thresh- old (see the electrical characteristics ). in adjustable mode, the current-limit threshold is precisely 1/20 thevoltage seen at ilim. for an adjustable threshold, con- nect a resistive divider from ref to gnd with ilim con- nected to the center tap. when adjusting the current limit, use 1% tolerance resistors with approximately 10? of divider current to prevent a significant increase of errors in the current-limit tolerance. output capacitor selection the output filter capacitor must have low enough effec-tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large-load transients, the outputcapacitor s size typically depends on how much esr is needed to prevent the output from dipping too lowunder a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor s size often depends on how much esr is needed to maintainan acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor s esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase arestaggered, resulting in lower output ripple voltage by reducing the total inductor ripple current. for 3- or 4-phase operation, the maximum esr to meet ripple requirements is: where total is the total number of active phases, t on is the calculated on-time per phase, and t trig is the trigger delay between the master s dh rising edge and the slave s dh rising edge. the trigger delay must be less than 1/(f sw x total ) for stable operation. the actual capacitance value required relates to the physi-cal size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, onceenough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). r vl vv t v t esr ripple in total out on total out trig ?? () 2 ? r v i esr step load max ? () i i lir limit low load max total () () > ?? ? ?? ? ? ?? ? ?? ? 1 2 v il cv soar load max total out out () () ? 2 2 v li vk v t cv vvk v t i c vk v t sag load max out in off min out out in out in off min load max out out in off min = ? ?? ? ?? ? ? ?? ?? ?? ?? + ?? ? ?? ? + ?? ? ?? ? ?? ? ?? ? + ?? ?? ?? ?? () () () () () () () ? ? 2 2 2 2 2 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 33 output capacitor stability considerations for quick-pwm controllers, stability is determined bythe value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: and: where c out is the total output capacitance, r esr is the total equivalent-series resistance, r sense is the current-sense resistance, a vps is the voltage-positioning gain, and r pcb is the parasitic board resistance between the output capacitors and sense resistors.for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of publication have typical esr-zero frequencies below 50khz. for example, the esr needed to support a 30mv p-p ripple in a 40a design is 30mv/(40a 0.3) = 2.5m . four 330?/2.5v panasonic sp (type xr) capacitors in paral-lel provide 2.5m (max) esr. their typical combined esr results in a zero at 40khz.ceramic capacitors have a high esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series pc board resistance to ensure stability. when only using ceramic output capacitors, output overshoot (v soar ) typically deter- mines the minimum output capacitance requirement.their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load con- ditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. the efficiency penalty for operating at 550khz is about 5% when compared to the 300khz circuit, primarily due to the high-side mosfet switching losses. unstable operation manifests itself in two related butdistinctly different ways: double-pulsing and feedback loop instability. double-pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time periodhas expired. double-pulsing is more annoying than harmful, resulting in nothing worse than increased out- put ripple. however, it can indicate the possible pres- ence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple currentrequirement (i rms ) imposed by the switching currents. the multiphase quick-pwm controllers operate out-of-phase, while the quick-pwm slave controllers provide selectable out-of-phase or in-phase on-time triggering. out-of-phase operation reduces the rms input current by dividing the input current between several stag- gered stages. for duty cycles less than 100%/ outph per phase, the i rms requirements may be determined by the following equation:where outph is the total number of out-of-phase switch- ing regulators. the worst-case rms current requirementoccurs when operating with v in = 2 outph v out . at this point, the above equation simplifies to i rms = 0.5 i load / outph . for most applications, nontantalum chemistries (ceramic,aluminum, or os-con ) are preferred due to their resis- tance to inrush surge currents typical of systems with amechanical switch or connector in series with the input. if the quick-pwm controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than 10 c temperature rise at the rms input current for optimal cir-cuit longevity. i i v vv v rms load outph in outph out in outph out = ?? ? ?? ? ? ? () rr ar r eff esr vps sense pcb =+ + f rc esr eff out = 1 2 f f esr sw os-con is a trademark of sanyo. downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 34 ______________________________________________________________________________________ power mosfet selection most of the following mosfet guidelines focus on thechallenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at bothv in(min) and v in(max) . calculate both of these sums. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher than the losses at v in(max) , consider increasing the size of n h (reducing r ds(on) but with higher c gate ). conversely, if the losses at v in(max) are significantly higher than the losses at v in(min) , consider reducing the size of n h (increasing r ds(on) to lower c gate ). if v in does not vary over a wide range, the minimum power dissipation occurs where theresistive losses equal the switching losses. choose a low-side mosfet that has the lowest possi- ble on-resistance (r ds(on) ), comes in a moderate- sized package (i.e., one or two so-8s, dpak, ord 2 pak), and is reasonably priced. ensure that the dl gate driver can supply sufficient current to support thegate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side mos- fet turning on; otherwise, cross-conduction problems can occur (see the mosfet gate driver section). mosfet power dissipation worst-case conduction losses occur at the duty factorextremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at theminimum input voltage: where total is the total number of phases. generally, a small high-side mosfet is desired toreduce switching losses at high input voltages. however, the r ds(on) required to stay within package power dissipation often limits how small the mosfetcan be. again, the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high- side switching losses do not usually become an issueuntil the input is greater than approximately 15v. calculating the power dissipation in high-side mosfet (n h ) due to switching losses is difficult since it must allow for difficult quantifying factors that influence theturn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss calculationprovides only a very rough estimate and is no substi- tute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c rss is the reverse transfer capacitance of n h and i gate is the peak gate-drive source/sink current (1a typ).switching losses in the high-side mosfet can become an insidious heat problem when maximum ac adapter voltages are applied due to the squared term in the c v in 2 f sw switching-loss equation. if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when biased fromv in(max) , consider choosing another mosfet with lower parasitic capacitance.for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage:the worst-case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to pro-tect against this possibility, you can overdesign the circuit to tolerate:where i valley(max) is the maximum valley current allowed by the current-limit circuit, including thresholdtolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward voltage low enough to prevent the low-side mosfet bodydiode from turning on during the dead time. as a gen- eral rule, select a diode with a dc current rating equal to 1/3 of the load current-per-phase. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate charging requirements ofthe high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving ii i i i lir load total valley max inductor total valley max load max =+ ?? ? ?? ? =+ ?? ? ?? ? () () () ? 2 2 pd n resistive v v i r l out in max load total ds on () () () =? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? 1 2 pd n switching v cf i i h in max rss sw gate load total () ( ) () = ?? ? ?? ? ?? ? ?? ? 2 pd n resistive v v i r h out in load total ds on () () = ?? ? ?? ? ?? ? ?? ? 2 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 35 medium-sized mosfets. however, high-current appli-cations driving large, high-side, mosfets require boost capacitors larger than 0.1?. for these applica- tions, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high-side mosfet s gates: where n is the number of high-side mosfets used forone regulator, and q gate is the gate charge specified in the mosfet s data sheet. for example, assume two irf7811w n-channel mosfets are used on the highside. according to the manufacturer s data sheet, a single irf7811w has a maximum gate charge of 24nc(v gs = 5v). using the above equation, the required boost capacitance would be:selecting the closest standard value, this example requires a 0.22? ceramic capacitor. current-balance compensation (cci) the current-balance compensation capacitor (c cci ) integrates the difference between the main and sec-ondary current-sense voltages. the internal compensa- tion resistor (r cci = 20k ) improves transient response by increasing the phase margin. this allows thedynamics of the current balance loop to be optimized. excessively large capacitor values increase the inte- gration time constant, resulting in larger current differ- ences between the phases during transients. excessively small capacitor values allow the current loop to respond cycle-by-cycle but can result in small dc current variations between the phases. likewise, excessively large resistor values can also cause dc current variations between the phases. small resistor values reduce the phase margin, resulting in marginal stability in the current-balance loop. for most applica- tions, a 470pf capacitor from cci to the switching reg- ulator s output works well. connecting the compensation network to the output(v out ) allows the controller to feed forward the output voltage signal, especially during transients. to reducenoise pickup in applications that have a widely distrib- uted layout, it is sometimes helpful to connect the com- pensation network to the quiet analog ground rather than v out . setting voltage positioning voltage positioning dynamically lowers the output volt-age in response to the load current, reducing the processor s power dissipation. when the output is loaded, an operational amplifier (figure 5) increasesthe signal fed back to the quick-pwm controller s feed- back input. the adjustable amplification allows the useof standard, current-sense resistor values, and signifi- cantly reduces the power dissipated since smaller cur- rent-sense resistors can be used. the load transient response of this control loop is extremely fast, yet well controlled, so the amount of voltage change can be accurately confined within the limits stipulated in the microprocessor power-supply guidelines. the voltage-positioned circuit determines the load current from the voltage across the current-sense resistors (r sense = r cm = r cs ) connected between the inductors and output capacitors, as shown in figure 10. the voltagedrop can be determined by the following equation: where sum is the number of phases summed together for voltage-positioning feedback, and total is the total number of active phases. when the slave controller isdisabled, the current-sense summation maintains the proper voltage-positioned slope. select the positive input summing resistors so r fbs = r f and r a = r b . minimum input voltage requirements and dropout performance the nonadjustable minimum off-time one-shot and thenumber of phases restrict the output voltage adjustable range for continuous-conduction operation. for best dropout performance, use the slower (200khz) on-time settings. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. manufacturing tolerances and internal propagation delays introduce an error to the ton k factor. this error is greater at higher fre- quencies (table 6). also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the v sag equation in the design procedure section). the absolute point of dropout is when the inductor cur-rent ramps down during the minimum off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). the ratio h = ? i up / ? i down is an indicator of the ability to vair a r r vps vps load sense vps sum f total b = = c xnc mv f bst == 224 200 024 . c nxq mv bst gate = 200 downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 36 ______________________________________________________________________________________ slew the inductor current higher in response toincreased load, and must always be greater than 1. as h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle and v sag greatly increases unless additional output capacitance is used.a reasonable minimum value for h is 1.5, but adjusting this up or down allows tradeoffs between v sag , output capacitance, and minimum operating voltage. for agiven value of h, the minimum operating voltage can be calculated as: where outph is the total number of out-of-phase switch- ing regulators, v vps is the voltage-positioning droop, v drop1 and v drop2 are the parasitic voltage drops in the discharge and charge paths (see the on-time one- shot (ton) section), t off(min) is from the electrical characteristics , and k is taken from table 6. the absolute minimum input voltage is calculated with h = 1.if the calculated v in(min) is greater than the required min- imum input voltage, then reduce the operating frequencyor add output capacitance to obtain an acceptable v sag . if operation near dropout is anticipated, calculate v sag to be sure of adequate transient response. dropout design example:v fb = 1.4v k min = 3? for f sw = 300khz t off(min) = 400ns v vps = 3mv/a 30a = 90mv v drop1 = v drop2 = 150mv (30a load) h = 1.5 and outph = 2 calculating again with h = 1 gives the absolute limit ofdropout: therefore, v in must be greater than 4.1v, even with very large output capacitance, and a practical input voltagewith reasonable output capacitance would be 5v. vx vm v m v xs x s mv mv mv v in min () . (. . / . . = + ?? ? ?? ? ++ = 2 1 4 90 150 1 2 04 10 30 150 150 90 4 07 - - - ? vx vm v m v xs x s mv mv mv v in min () . (. . / . . = + ?? ? ?? ? ++ = 2 1 4 90 150 1 2 04 15 30 150 150 90 4 96 - - - ? v vv v hxt k vvv in min outph fb vps drop outph off min drop drop vps () () = + ?? ? ?? ? ?? ?? ? ? ?? ?? ? ? ++ - - - 1 21 1 main phase second phase pc board trace resistance error comparator r f r a r a r b r b oain+ oain- fb pc board trace resistance cpu sensepoint cmp cmn csp csn l1 r sense r fbs l2 r sense max1544 figure 10. voltage-positioning gain downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 37 applications information pc board layout guidelines careful pc board layout is critical to achieve lowswitching losses and clean, stable operation. the switching power stage requires particular attention (figure 11). if possible, mount all of the power compo- nents on the topside of the board with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable,jitter-free operation. 2) connect all analog grounds to a separate solid copper plane, which connects to the gnd pin ofthe quick-pwm controller. this includes the v cc bypass capacitor, ref and gnds bypass capaci-tors, compensation (cc_) components, and the resistive dividers connected to ilim and ofs. 3) each slave controller should also have a separate analog ground. return the appropriate noise-sen-sitive slave components to this plane. since the reference in the master is sometimes connected to the slave, it may be necessary to couple the analog ground in the master to the analog ground in the slave to prevent ground offsets. a low-value ( 10 ) resistor is sufficient to link the two grounds. 4) keep the power traces and load connections short. this is essential for high efficiency. the use of thickcopper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. 5) keep the high-current, gate-driver traces (dl, dh, lx, and bst) short and wide to minimize traceresistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 6) c_p, c_n, oain+, and oain- connections for cur- rent limiting and voltage positioning must be madeusing kelvin-sense connections to guarantee the current-sense accuracy. 7) when trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path tobe made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low-side mosfet or between theinductor and the output filter capacitor. 8) route high-speed switching nodes away from sensitive analog areas (ref, ccv, cci, fb, c_p,c_n, etc). make all pin-strap control input connec- tions ( shdn , ilim, skip , sus, s_, ton) to analog ground or v cc rather than power ground or v dd . layout procedure place the power components first, with ground termi-nals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connectionson the top layer with wide, copper-filled areas. 1) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short andwide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic). 2) group the gate-drive components (bst diodes and capacitors, v dd bypass capacitor) together near the controller ic. 3) make the dc-to-dc controller ground connections as shown in the standard application circuits . this diagram can be viewed as having four sepa-rate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd pin and v dd bypass capacitor go; the master s analog ground plane, where sensitive analog components, the master s gnd pin, and v cc bypass capacitor go; and the slave s analog ground plane, where the slave s gnd pin and v cc bypass capacitor go. the mas- ter s gnd plane must meet the pgnd plane only at a single point directly beneath the ic. similarly,the slave s gnd plane must meet the pgnd plane only at a single point directly beneath the ic. therespective master and slave ground planes should connect to the high-power output ground with a short metal trace from pgnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 4) connect the output power planes (v core and system ground planes) directly to the output filtercapacitor positive and negative terminals with multiple vias. place the entire dc-to-dc converter circuit as close to the cpu as is practical. chip information transistor count: 11,015process: bicmos downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 38 ______________________________________________________________________________________ main phase inductor power ground output secondary phase input cpu kelvin sense vias under the sense resistor (refer to evaluation kit) c out c in c in c in c in c in c in c out c out c out c out c out inductor r sense r sense vias to power ground connect the exposed pad to analog gnd connect gnd and pgnd to the controller at one point only as shown place controller on back side when possible, using the ground plane to shield the ic from emi power ground (2nd layer) power ground (2nd layer) via to analog ground figure 11. pc board layout example downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 39 input*7v to 24v output v cc vrokshdn ofs power good off on d0 dac inputs suspend inputs (four-level logic) l1 c bst1 0.22 f n h1 n h2 n l1 c in c2 1 f c ref 0.22 f r10 10 r11 100k c ccv 47pf c cci 470pf c bst2 0.22 f r7182k 1% r6 1.65k 1% r11.65k 1% 5v bias supply c12.2 f c out c out *lower input voltages require additional input capacitance. bstdiodes ovpgnd timeccv r sense1 1.0m n l2 r6 20k 1% r8 100k 1% r4 1k 1% r51k 1% power groundanalog ground max1544 u1 c in ref ton ref v cc (ovp enabled) r2 1k 1% r31k 1% r time 64.9k d1 d2 d3 d4 s0 s1 l2 r sense2 1.0m bstm dhm lxm dlm pgnd gnd cmn cmp v+ oain+ oain- ref (300khz) fb cci csp csn bsts dhs lxs dls gnds v dd skip ilim r9 22.6k 1% c ref 0.22 f skip pwm figure 12a. standard amd desktop 70a application circuit (1st and 2nd phases max1544 master) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies 40 ______________________________________________________________________________________ input*7v to 24v output v cc polton ilim float (300khz) ref (master) comp output l3 c bst3 0.22 f n h3 n l3 c in c6 0.22 f r12 10 r comp1 20k c comp1 270pf r1849.9k r17 200k c9 100pf r13 100 r14 100 r15 100 r16 100 c71000pf c8 1000pf 5v bias supply c51 f dlm (master) cmp cmn connect to max1544 (see figure 12a) c out power groundanalog ground (master) *lower input voltages require additional input capacitance. d bst3 connect to max1544 (see figure 12a) dd limittrig skip (master) r sense3 1.0m d1 1n4148 max1980 u2 bst dh lx dl pgnd gnd cs+ cs- v+ cm+ cm- v dd figure 12b. standard amd desktop 70a application circuit (3rd phase max1980 slave) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 41 input*7v to 24v output v cc polton ilim float (300khz) ref (master) comp output l4 c bst4 0.22 f n h4 n l4 c in c11 0.22 f r19 10 r comp2 20k c comp2 270pf r2549.9k r24 200k c14 100pf r20 100 r21 100 r22 100 r23 100 c121000pf c13 1000pf 5v bias supply c101 f dls (master) csp csn connect to max1544 (see figure 12a) c out power groundanalog ground (master) *lower input voltages require additional input capacitance. d bst4 connect to max1544 (see figure 12a) dd limittrig skip (master) r sense4 1.0m d2 1n4148 max1980 u3 bst dh lx dl pgnd gnd cs+ cs- v+ cm+ cm- v dd figure 12c. standard amd desktop 70a application circuit (4th phase max1980 slave) downloaded from: http:///
max1544 dual-phase, quick-pwm controller for amd hammer cpu core power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 42 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l c 1 2 21-0141 package outline36,40l qfn thin, 6x6x0.8 mm 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: max. min. nom. t3666-1 3.70 3.60 3.80 d2 max. nom. min. e2 codes pkg. exposed pad variations common dimensions 10. warpage shall not exceed 0.10 mm. t4066-1 4.00 4.10 4.20 4.00 4.20 4.10 3.80 3.70 3.60 c 2 2 21-0141 package outline36, 40l qfn thin, 6x6x0.8 mm downloaded from: http:///

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